1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of field effect transistors having epitaxially grown raised drain and source regions so as to provide extremely shallow PN junctions.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for logic circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on an appropriate substrate.
Typically, a MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed at an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region. The conductivity of the channel region is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on the dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length.
Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of a specified control voltage to the gate electrode, the conductivity of the channel region substantially determines the characteristics of the MOS transistors. For this reason, the channel length represents a dominant design criterion and a size reduction thereof provides increased operating speed of the integrated circuits. The shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith which have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors.
One problem in this respect is the requirement of extremely shallow PN junctions. That is, the depth of the source and drain regions with respect to an interface formed by the gate insulating layer and the channel region has to be decreased as the channel length is reduced to maintain the required controllability of the conductive channel. The depth of the source and drain regions substantially determines the sheet resistance thereof, which may not be arbitrarily reduced by correspondingly increasing the dopant concentration in the source and drain regions, since an extremely high dopant concentration may give rise to increased leakage currents. Furthermore, the dopants implanted into these regions at very high concentrations may not be completely activated by conventional rapid thermal anneal processes without negatively affecting the overall dopant profile within the source and drain regions. That is, for a desired channel length, defined by the PN junctions, an increased dopant concentration requires higher temperatures and/or a prolonged duration of the corresponding anneal cycles, thereby, however, influencing the dopant profile forming the PN junctions by the inevitable thermal diffusion of the dopants, which finally may lead to a non-acceptable variation of the finally achieved channel length.
In an attempt to further reduce the sheet resistance of the drain and source regions, the conductivity thereof is frequently increased by forming a metal silicide of superior conductivity compared to a highly doped silicon. However, since the penetration depth of the metal silicide is restricted by the depth of the PN junctions, the improvement in conductivity in these regions is therefore coupled to the depth of the corresponding PN junctions. Moreover, in many CMOS technologies, a corresponding metal silicide is simultaneously formed on the gate electrode, wherein a shallow junction depth therefore also creates a very shallow metal silicide in the gate electrode, thereby providing only limited improvement in gaining superior gate electrode conductivity.
In one promising approach, extremely shallow source and drain regions may be formed by raising the source and drain regions above the gate insulation layer/channel region interface and maintaining the drain/source dopant concentration at an acceptable level while providing the possibility of forming highly conductive metal silicide regions without being restricted by the actual depth of the PN junctions due to the increased size of the raised drain and source regions.
With reference to FIGS. 1a-1c, a typical conventional process flow for forming raised drain and source regions will now be described in more detail. FIG. 1a schematically shows a cross-sectional view of a field effect transistor 100 at an early manufacturing stage. The transistor 100 comprises the substrate 101, for instance a bulk silicon substrate or a silicon-on-insulator (SOI) substrate including a buried insulating layer. Above the substrate 101, a substantially crystalline layer 102 is formed with a thickness that is appropriate for forming PN junctions and a channel region therein. For instance, the transistor 100 may represent an SOI transistor with a thickness of the silicon layer 102 in the range of approximately 20-100 nm.
A gate electrode 104, comprised of polysilicon, is formed above the silicon layer 102 and is separated therefrom by a gate insulation layer 103. The gate insulation layer 103 may be formed in sophisticated devices by a nitrogen-containing silicon dioxide layer with a thickness of approximately 0.6-4 nm. The residue 105 of an anti-reflective coating covers a top surface 104a of the gate electrode 104, while the sidewalls 104b thereof are covered by an oxide liner 106.
Moreover, adjacent to the liner 106 are formed sidewall spacer elements 107 comprised of a material, such as silicon nitride, that exhibits a moderately high etch selectivity with respect to the underlying oxide liner 106 so that the spacers 107 may be readily removed after a selective epitaxial growth process.
The transistor 100 as shown in FIG. 1a may be formed in accordance with the following process flow. The substrate 101 may be obtained by a manufacturer of respective substrates in the form of a silicon bulk substrate or in the form of an SOI substrate, wherein the SOI substrate may comprise a crystalline silicon layer as the layer 102 that may be formed in accordance with well-established wafer bonding techniques. Thereafter, an insulating layer is formed having a thickness and a composition that are appropriate for forming the gate insulation layer 103. To this end, sophisticated oxidation and/or deposition techniques may be used as are well established in the art.
Thereafter, a polysilicon layer of appropriate thickness is deposited by low pressure chemical vapor deposition. Next, an anti-reflective coating (ARC), for instance comprised of silicon oxynitride, and a resist layer are deposited and are patterned by sophisticated photolithography to form an etch mask for a subsequent anisotropic etch process for patterning the gate electrode 104 from the deposited polysilicon layer. After patterning the gate electrode 104, the residual ARC layer remains as the layer 105 on the top surface 104a of the gate electrode 104.
Thereafter, the gate insulation layer 103 may be patterned and subsequently the oxide liner 106 may be formed by an appropriately designed oxidation process. The sidewall spacers 107 may then be formed by well-established techniques, including the deposition, for instance by plasma enhanced chemical vapor deposition, of a silicon nitride layer of a specified thickness and a subsequent anisotropic etch process, which reliably stops on and in the liner oxide 106, thereby leaving the spacers 107. A width 107a of the spacer 107 is readily controllable by appropriately adjusting the thickness of the silicon nitride layer. Hence, a lateral extension of epitaxial growth regions adjacent to the gate electrode 104 is substantially determined by the spacer width 107a. Finally, the liner 106 may be removed at exposed portions to provide a substantially crystalline surface of the layer 102 for an epitaxial growth process.
FIG. 1b schematically shows the device 100 with selectively grown silicon regions 108 above the silicon layer 102, wherein a lateral distance of the regions 108 from the gate electrode 104 substantially corresponds to the spacer width 107a (see FIG. 1a) plus the minimal thickness of the liner oxide 106. Moreover, the spacers 107, the liner 106 and the residual ARC layer 105 are removed. The process for forming the crystalline regions 108, which may contain a specified dopant material, typically involves a selective epitaxial growth technique. This growth technique of a semiconductor material is a deposition technique in which the deposited material layer forms a crystalline structure in conformity with the crystalline structure of the underlying material, acting as a template, as long as the deposited material is able to form a lattice that is sufficiently similar in structure and lattice spacing to the lattice of the underlying material. Furthermore, the deposition parameters are selected in such a manner that the semiconductor material adheres mainly to the atoms of the ordered crystalline surface of the layer 102 rather than to the dielectric non-crystalline surfaces of the spacers 107 and the residual ARC layer 105. Thereafter, the spacers 107, the liner 106 and the layer 105 are removed by well-established highly selective etch processes. Subsequently the device 100 may be subjected to an ion implantation sequence 120 including, for instance, a halo and extension implantation to form extension regions 113 in the layer 102 and also form implantation regions 113 in the regions 108. Following the implantation 120, an anneal process may be performed, thereby activating dopants and substantially re-crystallizing implantation-induced damage in the layer 102 and the regions 108.
FIG. 1c schematically shows the device 100 in a further advanced manufacturing stage. Here, the device 100 comprises a spacer 117 formed on a liner 116. The spacer 117 may be comprised of silicon nitride, while the liner 116 may be made of silicon dioxide. Moreover, metal silicide regions 118 are formed in the epitaxially grown regions 108 and form in combination source and drain regions 114. A further metal silicide region 115 is formed in the gate electrode 104. Typically, the spacer 117 and the liner 116 may be formed substantially in the same way as is previously described with respect to the spacer 107 and the liner 106. The silicide regions 115 and 118 may be formed commonly or separately in accordance with well-established silicidation regimes, wherein the spacer 117 prevents an undesired creation of a conductive path between the gate electrode 104 and the drain and source regions 114 during the formation of the metal silicide regions 115 and 118.
As a result, the above-described process flow enables the formation of required shallow PN junctions in the form of the extensions 113, while nevertheless providing a low contact resistance to the drain and source regions 114 by providing the additional selectively grown silicon regions 108, which may be used to receive a highly conductive metal silicide, wherein the silicidation process does not adversely affect the extensions 113, nor is the silicidation process restricted by the depth of the extensions 113 and the drain and source regions 114.
Although the process flow described above provides significant improvements in forming raised drain and source regions, in highly sophisticated applications requiring critical dimensions, i.e., a gate length 104l of the gate electrode 104 of approximately 50 nm and even less, the approach with removable spacers, i.e., the spacers 107, and with a reliable coverage of the gate electrode, renders it increasingly difficult to also appropriately pattern the gate electrode 104 by means of the residual ARC layer 105. In other words, since the residual ARC layer 105 is important for both the patterning of the gate electrode 104 and the reliable coverage thereof in the subsequent selective epitaxial growth process, the conventional ARC layer 105 may not suffice, as its integrity may suffer during the patterning process for the gate electrode 104 owing to, for instance, a resist mask of reduced thickness and other requirements as may be necessary in the advanced 193 nm lithography. Consequently, the coverage of the top surface 104a with an ARC layer meeting the strict requirements of the preceding lithography, resist trim and gate etch processes designed for highly scaled devices may not be reliably guaranteed.
In view of the above situation, a need therefore exists for an improved technique that enables the formation of raised source and drain regions by selective epitaxial growth while still offering the potential for device scaling.